/*
 * Device Tree Source for the r8a77995 SoC
 *
 * Copyright (C) 2016 Renesas Electronics Corp.
 * Copyright (C) 2017 Glider bvba
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/clock/renesas-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "renesas,r8a77995";
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		a53_0: cpu@0 {
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0>;
			device_type = "cpu";
			power-domains = <&sysc 5>;
			next-level-cache = <&L2_CA53>;
			enable-method = "psci";
		};

		L2_CA53: cache-controller-1 {
			compatible = "cache";
			power-domains = <&sysc 21>;
			cache-unified;
			cache-level = <2>;
		};
	};

	extal_clk: extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	scif_clk: scif {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gic: interrupt-controller@f1010000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0xf1010000 0 0x1000>,
			      <0x0 0xf1020000 0 0x20000>,
			      <0x0 0xf1040000 0 0x20000>,
			      <0x0 0xf1060000 0 0x20000>;
			interrupts = <GIC_PPI 9
					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&cpg CPG_MOD 408>;
			clock-names = "clk";
			power-domains = <&sysc 32>;
			resets = <&cpg 408>;
		};

		timer {
			compatible = "arm,armv8-timer";
			interrupts = <GIC_PPI 13
					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
				     <GIC_PPI 14
					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
				     <GIC_PPI 11
					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
				     <GIC_PPI 10
					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
		};

		rwdt: watchdog@e6020000 {
			compatible = "renesas,r8a77995-wdt",
				     "renesas,rcar-gen3-wdt";
			reg = <0 0xe6020000 0 0x0c>;
			clocks = <&cpg CPG_MOD 402>;
			power-domains = <&sysc 32>;
			resets = <&cpg 402>;
			status = "disabled";
		};

		pmu_a53 {
			compatible = "arm,cortex-a53-pmu";
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		};

		cpg: clock-controller@e6150000 {
			compatible = "renesas,r8a77995-cpg-mssr";
			reg = <0 0xe6150000 0 0x1000>;
			clocks = <&extal_clk>;
			clock-names = "extal";
			#clock-cells = <2>;
			#power-domain-cells = <0>;
			#reset-cells = <1>;
		};

		rst: reset-controller@e6160000 {
			compatible = "renesas,r8a77995-rst";
			reg = <0 0xe6160000 0 0x0200>;
		};

		pfc: pfc@e6060000 {
			compatible = "renesas,pfc-r8a77995";
			reg = <0 0xe6060000 0 0x508>;
		};

		prr: chipid@fff00044 {
			compatible = "renesas,prr";
			reg = <0 0xfff00044 0 4>;
		};

		sysc: system-controller@e6180000 {
			compatible = "renesas,r8a77995-sysc";
			reg = <0 0xe6180000 0 0x0400>;
			#power-domain-cells = <1>;
		};

		scif2: serial@e6e88000 {
			compatible = "renesas,scif-r8a77995",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6e88000 0 64>;
			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 310>,
				 <&cpg CPG_CORE 16>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			power-domains = <&sysc 32>;
			resets = <&cpg 310>;
			status = "disabled";
		};
	};
};
